/*
 * Copyright 2024 NXP
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <zephyr/devicetree.h>
#include <zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h>

#define REGION_FLEXSPI2_BASE_ADDRESS   0x14000000
#define REGION_FLEXSPI2_SIZE           0x04000000
#define REGION_DTCM_BASE_ADDRESS       0x30000000
#define REGION_DTCM_SIZE               0x00020000
#define REGION_SRAM2_SHM_BASE_ADDRESS  0x20500000
#define REGION_SRAM2_SHM_SIZE          0x00008000
#define REGION_FLEXSPI_BASE_ADDRESS    0x38000000
#define REGION_FLEXSPI_SIZE            0x08000000
#define REGION_PERIPHERAL_BASE_ADDRESS 0x50000000
#define REGION_PERIPHERAL_SIZE         0x40000000

static const struct arm_mpu_region mpu_regions[] = {
	MPU_REGION_ENTRY("FLEXSPI2", REGION_FLEXSPI2_BASE_ADDRESS,
			 REGION_RAM_ATTR(REGION_FLEXSPI2_BASE_ADDRESS, REGION_FLEXSPI2_SIZE)),
	MPU_REGION_ENTRY("FLEXSPI", REGION_FLEXSPI_BASE_ADDRESS,
			 REGION_FLASH_ATTR(REGION_FLEXSPI_BASE_ADDRESS, REGION_FLEXSPI_SIZE)),
	MPU_REGION_ENTRY("DTCM", REGION_DTCM_BASE_ADDRESS,
			 REGION_RAM_NOCACHE_ATTR(REGION_DTCM_BASE_ADDRESS, REGION_DTCM_SIZE)),
	MPU_REGION_ENTRY(
		"SRAM2_SHM", REGION_SRAM2_SHM_BASE_ADDRESS,
		REGION_RAM_NOCACHE_ATTR(REGION_SRAM2_SHM_BASE_ADDRESS, REGION_SRAM2_SHM_SIZE)),
	MPU_REGION_ENTRY(
		"PERIPHERAL", REGION_PERIPHERAL_BASE_ADDRESS,
		REGION_DEVICE_ATTR(REGION_PERIPHERAL_BASE_ADDRESS, REGION_PERIPHERAL_SIZE)),
};

const struct arm_mpu_config mpu_config = {
	.num_regions = ARRAY_SIZE(mpu_regions),
	.mpu_regions = mpu_regions,
};
